The present invention generally relates to methods and resulting structures for semiconductor devices, and more specifically, to front-end-of-line shape merging cell placement and optimization.
The individual components of an integrated circuit (IC) are extremely small and its production demands precision at an atomic level. IC fabrication is a complex process during which electronic circuits are created in and on a wafer made out of very pure semiconducting material, typically silicon. The manufacturing is a multiple-step sequence which can be divided into two major processing stages, namely front-end-of-line (FEOL) processing and back-end-of-line (BEOL) processing. FEOL refers to the construction of the components of the IC directly inside the wafer. FEOL is the first portion of IC fabrication where the individual devices (such as transistors, capacitors, resistors, etc.) are patterned in the semiconductor. FEOL generally covers all steps up to the deposition of metal interconnect layers. FEOL contains all steps of CMOS fabrication needed to form fully isolated CMOS elements. The processes can include, but are not limited to, selecting the type of wafer to be used, chemical-mechanical planarization and cleaning of the wafer, shallow trench isolation (STI), transistor channel formation, gate module formation, and source and drain module formation.